Two-layer model for source resistance in selectively doped heterojunction transistors

The selectively doped heterojunction transistor (SDHT) is currently under development for logic applications requiring very high speed at very low power dissipation. A crucial part of the device is a heterojunction in which a highly doped n-Al(0-3)Ga(0.7)As is in contact with undoped high-purity GaAs. Conduction electrons are transferred across the heterointerface, and a degenerate two-dimensional electron gas (2DEG) of extremely high mobility is produced. The conducting channel of the SDHT is formed with the aid of the 2DEG, which is controlled by the field effect. A one-layer model (1LM) based on the transmission-line method has been used to assess the role of the metal-semiconductor contact. However, in SDHT's the 1LM can lead to a serious underestimate of parasitic resistance. The present paper has the objective to discuss the magnitude and origin of this error, and to outline a more sophisticated model of SDHT source resistance. The new model represents a two-layer model concept.