A single transistor electrically alterable cell

A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electron injection while erasing is performed via Fowler-Nordheim tunneling through a thin oxide (100-A) region. The memory cell requires only one transistor because the write and erase voltages range between 15-20 and 25-30 V, respectively. The writeability of the cell is enhanced by the thin oxide region and dependent on the proximity of this region to the channel of the DMOS transistor.