An ac-powered experimental memory circuit with a resistively loaded sense circuit
Abstract
The design and fabrication of an ac-powered experimental memory circuit for Josephson cache memories are reported. The circuit contains a memory cell array and a sense circuit. The sense circuit consists of RCJL gates, symmetrical three-junction sense gates, and transmission lines. An experimental memory circuit has been fabricated by 2-micron Pb-alloy processes. A proper circuit operation has been verified using a bipolar trapezoidal waveform current. A + or - 23-percent sense current margin and a + or - 29-percent OR gate bias current margin were obtained. A typical 130-ps sense time was estimated for a 1-kbit memory by computer simulations.
- Publication:
-
IEEE Electron Device Letters
- Pub Date:
- May 1985
- DOI:
- 10.1109/EDL.1985.26121
- Bibcode:
- 1985IEDL....6..267H
- Keywords:
-
- Alternating Current;
- Josephson Junctions;
- Memory (Computers);
- Network Synthesis;
- Random Access Memory;
- Access Time;
- Chips (Electronics);
- Logic Circuits;
- Electronics and Electrical Engineering