A gallium arsenide overlapping-gate charge-coupled device

A new CCD fabrication process for producing an overlapping gate structure which permits submicrometer control of the gap size while using conventional lithography has been developed. This process has been used to fabricate four-phase 16-stage Schottky barrier CCD's on GaAs with charge transfer inefficiencies of less than 2 x 0.0001 at a 1-MHz clock rate, indicating that charge loss due to potential troughs between the gates has been essentially eliminated. This control of the gap permits the CCD channel to be of submicrometer thickness, which simplifies the integration of CCD's with high-speed devices requiring submicrometer channel thicknesses.