Signal processor chip implementation

Advances in technology have made it now possible to integrate very large microprocessors on a single chip. Two basic design methodologies are available, including gate array and custom design. The present paper is concerned with a signal processor (SP) chip which is based on a mixture of the two technologies. Involved is a high-density chip which requires little manual effort for its production. The SP is characterized by separate instruction and data memories. The SP consists of three main parts which operate simultaneously. These parts include the sequencer, the address generator, and the computer portion. The chip comprises a library of predesigned building blocks. Attention is given to a signal processor block diagram, the basic TTL gate, a two-input master-slave latch, the physical library, aspects of logical design, the multiplier basic cell and adder line organization, and physical design methodology.