Self-aligned MESFETs by a dual-level double-lift-off substitutional gate (DDS) technique for high-speed low-power GaAs ICs

A new self-aligned substitutional gate processing technique which involves dual-level resist patterning was developed for 75 mm (3 in.)-diameter GaAs MESFETs IC fabrication. The transconductance of 1-micron gate-length DDS E-MESFETs reached a maximum value of 280 mS/mm. E/R ring oscillators showed a 22 ps/gate propagation delay and a 34.5 fJ speed-power product. E/D ring oscillators had a 53 ps/gate propagation delay, a 12.5 fJ speed-power product and a power dissipation of 0.24 mW/gate at 300 K.