Digital transversal filter architecture
Abstract
A fast and efficient architecture is described for the realization of a pipelined, fully parallel digital transversal filter in VLSI. The order of summation is changed such that no explicit multiplication is seen, gated accumulators are used, and the coefficients are circulated. Estimates for the number of transistors needed for a CMOS implementation are given.
- Publication:
-
Electronics Letters
- Pub Date:
- January 1985
- DOI:
- 10.1049/el:19850060
- Bibcode:
- 1985ElL....21...86G
- Keywords:
-
- Digital Filters;
- Logic Design;
- Signal Processing;
- Chips (Electronics);
- Cmos;
- Transistors;
- Very Large Scale Integration;
- Electronics and Electrical Engineering