Latch-up effect in CMOS described

The latch-up effect was first discovered in a small-scale bipolar integrated circuit. As long as there are parasitic four-layer PNPN structures, under certain conditions, the latch-up effect can occur. Since bulk CMOS circuits are of four-layer structure, the latch-up effect is a failure mode which often occurs in them. With the improvement of integration and the reduction in component dimensions, the latch-up effect can become increasingly serious. Therefore, how to reduce or eliminate the latch-up effect and improve the reliability of CMOS circuits is a subject which has been getting more and more attention. The latch-up phemonenon in CMOS circuits is discussed, the conditions which produce it are analyzed, and proposals for preventative measures in design, industrial technology, and use are made.