Three-dimensional circuit layouts

Recent advances in fabrication technology have rendered imminent the fabrication of multilayer chips, wafers and circuit boards. This paper examines the savings in material and communication time afforded by the development of three-dimensional technology. In particular, derived are close upper and lower bounds on the volume and maximum wire length with which circuits can be realized in a multilayer medium. For example, it is found that the smallest volume of any three-dimensional layout of an N-device circuit is no more than (roughly) (AN)1/2, where A is the smallest area of any two-dimensional layout of the circuit. It is also showing how to efficiently transform a two-dimensional layout of area A and maximum wire length L into a three-dimensional layout of volume (roughly) V = A/H and maximum wire length L = L/H for moderate numbers of layers H. Two noteworthy features of the study are: (1) that, within logarithmic factors, the indicated savings can be realized with layouts that use the third dimension only for interconnect; and (2) that the indicated savings can be realized algorithmically we present polynomial-time algorithms that transform a given two-dimensional layout into a more efficient three-dimensional layout.