Threedimensional circuit layouts
Abstract
Recent advances in fabrication technology have rendered imminent the fabrication of multilayer chips, wafers and circuit boards. This paper examines the savings in material and communication time afforded by the development of threedimensional technology. In particular, derived are close upper and lower bounds on the volume and maximum wire length with which circuits can be realized in a multilayer medium. For example, it is found that the smallest volume of any threedimensional layout of an Ndevice circuit is no more than (roughly) (AN)1/2, where A is the smallest area of any twodimensional layout of the circuit. It is also showing how to efficiently transform a twodimensional layout of area A and maximum wire length L into a threedimensional layout of volume (roughly) V = A/H and maximum wire length L = L/H for moderate numbers of layers H. Two noteworthy features of the study are: (1) that, within logarithmic factors, the indicated savings can be realized with layouts that use the third dimension only for interconnect; and (2) that the indicated savings can be realized algorithmically we present polynomialtime algorithms that transform a given twodimensional layout into a more efficient threedimensional layout.
 Publication:

Massachusetts Inst. of Tech. Report
 Pub Date:
 June 1984
 Bibcode:
 1984mit..reptS....L
 Keywords:

 Chips (Electronics);
 Circuit Boards;
 Circuits;
 Fabrication;
 Layouts;
 Logarithms;
 Wafers;
 Algorithms;
 Dimensions;
 Functions (Mathematics);
 Polynomials;
 Transformations;
 Electronics and Electrical Engineering