Design study of floating point systolic VLSI chip
Abstract
The objective of this program was to investigate the feasibility of building a floating point processor (24-bit mantissa and 8-bit exponent) on a single ship based on the Hughes Research Laboratories (HRL) present 28-bit fixed point chip (Multiplication Oriented Processor or MOP chip). The plan was to generate any necessary cell logic, layout, or simulations in order to estimate the size of the chip and predict its performance. Since division and square root were not included in the HRL MOP chip, arithmetic algorithms for performing these operations were to be studied.
- Publication:
-
Final Report Hughes Research Labs
- Pub Date:
- March 1984
- Bibcode:
- 1984hrl..rept.....N
- Keywords:
-
- Central Processing Units;
- Chips (Electronics);
- Computer Design;
- Computer Systems Design;
- Floating Point Arithmetic;
- Very Large Scale Integration;
- Algorithms;
- Bits;
- Dividers;
- Exponents;
- Feasibility Analysis;
- Logic Design;
- Microelectronics;
- Newton-Raphson Method;
- Scalers;
- Electronics and Electrical Engineering