Electrical overstress protection of submicron devices

The objective of this program was to further define the electrical overstress (EOS) sensitivity characterization procedures for microelectric devices and to investigate the EOS sensitivity of micron and submicron linewidth circuit structures. Another objective was to investigate improved EOS protection schemes and evaluate their benefits versus performance and cost penalties. The approach chosen to achieve these objectives was to attempt to design input protection networks which would protect an MOS device fabricated from a submicron process from an electrostatic discharge (ESD) threat. The program included the definition of ESD threats, examination of the characteristics of existing input protection networks, a study of the factors which limit the effectiveness of protection networks, and consideration of alternate approaches to achieve ESD hardness. The limiting factors which are expected to determine the electrical overstress sensitivity of micron and submicron design rule microcircuit technologies were investigated using computer-aided modeling techiques. Network analysis codes were used to exercise lumped circuit analogs of the electrical and thermal properties of the devices under study when subjected to ESD stress. Simple time domain network analysis codes suitable for microcomputers were used and are discussed in the report. The minimum cross-sectional areas of aluminum and polysilicon interconnects and semiconductor devices which are capable of withstanding an ESD event were established. Two candidate submicron technologies were considered in this study, CMOS and NMOS.