Precision digital sampler

A precision digital sampler utilizes a sample rate clock providing pulses driving a tapped delay line where the total delay equals the Pulse Repetition Interval of the sample clock. The outputs of the tapped delay line are tied to a buffer register having a storage cell for each delay line tap. The data from the delay line is stored in the register on receipt of a command signal designated sample initiate command. In storing the outputs of the delay line, the state of the sample clock is known to the resolution of the taps. A decoder studies the states and the time for locating the leading edge of the sample clock is calculated. The calculated time is used by a control switching circuit to determine which tap should be enabled. The leading edge of the sample clock is thus enabled at the resolution of the delay line taps.