Circuit topology, signal propagation delay and the efficiency of VLSI circuits
Abstract
The effect of signal propagation delay and circuit topology on VLSI circuit performance is discussed. Topologies with the same function such that a circuit topology which is optimal under one delay assumption is suboptimal under another exist. Under constant signal propagation delay, or logarithmic delay, systolic search trees or fast permutation networks can be laid out to perform better if constant width wires are assumed. However, under logarithmic signal propagation delay with the required constant aspect ratio for wires the naive mesh layout is superior over every tree layout with respect to area and period. For the fast fourier transform, the naive mesh layout is superior over every layout for a fast permutation network like the cubeconnected cycles in area, area x period and the area x execution time. For a complete Nnode binary tree, with the wire aspect ratio and number of layers constants independent of N, it is impossible to lay out a complete Nnode binary tree using equal length wires.
 Publication:

NASA STI/Recon Technical Report N
 Pub Date:
 August 1984
 Bibcode:
 1984STIN...8520267V
 Keywords:

 Circuit Reliability;
 Signal Transmission;
 Time Lag;
 Topology;
 Vhsic (Circuits);
 Aspect Ratio;
 Electric Wire;
 Fast Fourier Transformations;
 Layouts;
 Width;
 Electronics and Electrical Engineering