Signal propagation delay, wire length distribution and the efficiency of VLSI circuits

Signal propagation delay in long wires of VLSI circuits is discussed. There are wire length distributions for which the logarithmic delay assumption entails at least an exponential increase in area over the constant wire width assumption for any layout with that distribution. Consequently, the wires need to get so much longer to achieve logarithmic delay that the absolute propagation delay turns out to be not improved over an original linear or quadratic propagation delay. Given that the wide wires have to be actually placed in a layout, the logaritmic delay requirement may not be implementable at all, and even if it could it would give no improvement in absolute time.