Development of short gate FET's

The goal of this work was to investigate the performance limit of the standard GaAs FET structure. During the contract period we have constructed an AsCl3 epitaxial system used to provide buffer layers for our FET structures, we have developed a submicron lithographic process using deep U.V. techniques and, using these techniques we have produced working .5 micron gate devices. In addition, we have investigated the gettering of substrates as a technique to improve the mobility of ion implanted layers. The result of this experiment showed a correlation between Hall mobilities and gettered substrates. Finally, a investigation of a self aligned source drain structure has commenced and several theoretical studies are reported.