Numerical simulation of hot-electron effects on source-drain burnout characteristics of GaAs power FETs

A High Speed Semiconductor Device Analysis (HISSDAY) computer program, based on the energy transport model, is used to numerically analyze various GaAs FET structures to gain physical insights and to establish potential design criteria for minimization of burnout phenomena. A major finding is the relationship between the spatial distribution of hot electrons in the gate-drain region and the degree of burnout tolerance. FET structures which effectively prevent hot electrons from reaching the drain edge demonstrate high burnout power. Recessed-gate structures alone do not prevent hot electrons from reaching the edge of the drain electrode and therefore cannot prevent or minimize source-drain burnout. Gate-to-drain surface-field considerations also indicate that whereas recessed-gate designs improve gate-drain avalanche breakdown voltages, recessed-channel and n⁺ ledge designs tend to degrade gate-drain avalanche breakdown voltages. The combination of recessed gate and n⁺ ledge or recessed channel (double-recess structure) is a central feature to designs which minimize both gate-drain avalanche and source-drain burnout. A feedback-system model of the source-drain burnout mechanism for all FET structures simulated is proposed. Significant source-drain burnout voltage degradation at large gate biases near pinchoff is clarified in terms of the strong sensitivity of the hot electron energy-density distribution to channel opening in conventional MESFETs.