Investigation of Interface States and Failure Mechanisms in Mnos Devices

The objective of this dissertation is to conduct a quantitative study of the interface state characteristics at Si-SiO(,2) interface and the failure mechanisms in the silicon MNOS nonvolatile memory devices under different write/erase (W/E) cycling conditions. The main thrust of this research is to quantitatively characterize the interface states in MNOS devices and to correlate the results of the measurements to the failure mechanisms in the exercised MNOS devices for W/E cycles up to 1 x 10('11) cycles. The Constant-Capacitance Deep Level Transient Spectroscopy (CC-DLTS) technique is employed for the first time to characterize the interface states in the MNOS device. The existing theory for the CC-DLTS technique is modified to analyze the interface state density and electron capture cross sections of the trap states at Si-SiO(,2) interface. An exact equivalent circuit model for the p('+)-gridded MNOS capacitors is developed to predict the high frequency C -V behavior in the exercised MNOS devices. The results show little change in the interface state density was observed for W/E cycles less than 1 x 10('7) and increased rapidly for W/E cycles greater than 1 x 10('7). For W/E cycles greater than 5 x 10('9), a gradual increase in interface state density with W/E cyclings was observed. The negative shift of threshold voltage in the exercised MNOS devices can be attributed to the creation of interface states for W/E cycles less than 10('9) and primarily due to the generation of interface states for W/E cycles exceeding 1 x 10('9). The increase in interface state densities and the degradation of the thin oxide layer after prolonged W/E cycling increase the back tunneling current which results in the increase of retention decay rate. Furthermore, mobility degradation in the inversion layer was observed in the MNOS transistors for W/E cycling exceeds 10('9). This is attributed to the generation of surface state densities. Improvement in retention and endurance of the MNOS transistors may be achieved by altering NH(,3)/SiH(,4) ratio, oxide thickness and annealing conditions. The scale-down Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure may enhance the performance of MNOS nonvolatile memory devices.