High voltage lateral power transisters: Theory and design

A new lateral device, the lateral bipolar field effect transistor or LABFET, is described. This device replaces the normal n+-drain diffusion, used in the typical double diffused MOS(DMOS) transistor with a p-type diffusion. This p-diffusion acts as the emitter of a low gain p-n-p bipolar transistor. The base of this device is the n-substrate or n-well, when the device is part of an integrated circuit. The base current is supplied by turning on the DMOS field effect transistor. The result is a conductivity modulated device, with all terminals on the top of the chip, a voltage withstand capability of 100 V and an on-state conductance of .71 Siemans per cm of gate width. This is comparable with conventional vertical FET devices. The static and dynamic characteristics of unit cell devices are presented with an explanation of the results and a description of the processing to produce them. Finally, suggestions are made which would allow the extension of this concept to a large device suitable for integration into a power integrated circuit.