Ultra-large scale integration

It is pointed out that ultra-large scale integration (ULSI) of 10 to the 7th to 10 to the 9th components in a single chip of silicon is governed by a hierarchy of limits. The levels of this hierarchy can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system. The present paper has the objective to project the future of integrated electronics by studying the five levels of theoretical, practical, and analogical limits which govern its progress. An investigation is conducted regarding the smallest allowable dimensions for integrated structures, taking into account transistors, resistors, and interconnections. The theoretical limits considered are based on the principles of solid-state science. The practical limits which depend upon manufacturing processes and equipment are also studied. Aspects of feature size are discussed along with the die size, packing efficiency, and the number of components per chip.