Design of GaAs 1k bit static RAM
Abstract
A 1k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to increase operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of speed, power, and operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far for practical application in cache or buffer memories.
- Publication:
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IEEE Transactions on Electron Devices
- Pub Date:
- September 1984
- DOI:
- Bibcode:
- 1984ITED...31.1139I
- Keywords:
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- Access Time;
- Gallium Arsenides;
- Integrated Circuits;
- Network Synthesis;
- Random Access Memory;
- Volt-Ampere Characteristics;
- Buffer Storage;
- Chips (Memory Devices);
- Fabrication;
- Logic Circuits;
- Logic Design;
- Electronics and Electrical Engineering