The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm
Abstract
Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes often requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.
- Publication:
-
IEEE Transactions on Computers
- Pub Date:
- October 1984
- Bibcode:
- 1984ITCmp..33..906H
- Keywords:
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- Algorithms;
- Biternary Code;
- Coding;
- Multiplication;
- Very Large Scale Integration;
- Channels (Data Transmission);
- Chips (Electronics);
- Deep Space Network;
- Metal Oxide Semiconductors;
- Electronics and Electrical Engineering