Computational geometry on a systolic chip

Systolic arrays are one- or two-dimensional arrangements of simple cells which are locally connected. The essential features of systolic cells are their simplicity, regularity, and modularity. Systolic architectures provide an answer to challenges related to increasing levels of circuit integration. Modularity makes it possible for the designer to decompose the system's architecture into building blocks which can be used repetitively with simple interfaces. An investigation is conducted regarding the gains in performance which can be expected from a systolic treatment of computational geometry. Arrays with a single string of cells, each connected to their one or two neighbors, are considered. A description of the general features of the geometric systolic array is presented, and systolic designs for several geometric problems are provided. Two distinct types of tasks are generally involved. One is concerned with the actual computation of geometric functions, while the other involves initiating and granting requests.