A radix 4 delay commutator for fast Fourier transform processor implementation

This paper describes the development of a semicustom delay commutator circuit to suppor the implementation of high speed fast Fourier transform processors based on the McCellan and Purdy radix 4 pipeline FFT algorithm. The delay commutator is a 108,000 transistor circuit comprising 12,288 shift register stages and approximately 2000 gates of random logic realized with 2.5 micrometer design rule CMOS standard cell technology. It operates at a 10 MHz clock rate which processes data at a 40 MHz rate. The delay commutator is suitable for implementing processors that compute transforms of 16, 64, 256, 1024, and 4096 (complex) points. It is implemented as a 4 bit wide data slice to facilitate concatenation to accomodate common data word sizes and to use a standard 48 pin dual-in-line package.