Folded gate - A novel logic gate structure

A new logic gate structure is proposed which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This 'folded' gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher than the speed of conventional direct-coupled field-effect transistor logic and a larger voltage swing.