Fundamental timing problems in testing MOS VLSI on modern ATE
Abstract
Most new VLSI test systems connect pulse drivers and high-impedance comparator circuits to the pins of the device under test through 50- or 90-ohm transmission lines that may be as long as 50 cm when 256 comparators are required. This can lead to serious problems in the case of MOS devices designed to drive capacitive loads. Unless timing measurements are made at the 50-percent level of the initial voltage step at the comparators and theoretical corrections are applied, MOS measurements can be in error by as much as 10 ns even though modern automatic test equipment can be adjusted to subnanosecond accuracy. It is shown here how timing corrections can be incorporated into current test programs. It is noted, however, that in order to meet future needs, 256-pin test heads have to be developed that present less than 20 pF of capacitance per pin of the device under test.
- Publication:
-
IEEE Design Test Computers
- Pub Date:
- August 1984
- Bibcode:
- 1984IDTC....1...90B
- Keywords:
-
- Automatic Test Equipment;
- Electronic Equipment Tests;
- Metal Oxide Semiconductors;
- Time Measurement;
- Very Large Scale Integration;
- Capacitance;
- Electrical Resistance;
- Impedance Measurement;
- Time Lag;
- Waveforms;
- Electronics and Electrical Engineering