Below 10 ps/gate operation with buried p-layer SAINT FETs
Abstract
GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be(+) implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parasitic capacitance.
- Publication:
-
Electronics Letters
- Pub Date:
- December 1984
- DOI:
- Bibcode:
- 1984ElL....20.1029Y
- Keywords:
-
- Field Effect Transistors;
- Gallium Arsenides;
- Gates (Circuits);
- Ion Implantation;
- Capacitance;
- Fabrication;
- P-Type Semiconductors;
- Performance Tests;
- Self Alignment;
- Time Lag;
- Very Large Scale Integration;
- Electronics and Electrical Engineering