Switching circuits for yield-enhancement of an array chip
Abstract
The McCanny and McWhirter (1983) method for the enhancement of bit-level systolic array chip yield has as a major limitation the necessary operation of all the configuration circuitry. The alternative approaches presently examined tolerate some defects in this circuitry, and attention is given to one scheme which appears to be especially effective.
- Publication:
-
Electronics Letters
- Pub Date:
- August 1984
- DOI:
- Bibcode:
- 1984ElL....20..667M
- Keywords:
-
- Chips (Electronics);
- Circuit Reliability;
- Fault Tolerance;
- Switching Circuits;
- Very Large Scale Integration;
- Arrays;
- Computer Components;
- Electronic Modules;
- Fail-Safe Systems;
- Logic Circuits;
- Yield;
- Electronics and Electrical Engineering