Waferscale integration of systolic arrays
Abstract
VLSI technologies are fast developing waferscale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind waferscale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating waferscale systems "around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NPcomplete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, faulttolerant systems and planar geometry.
 Publication:

Unknown
 Pub Date:
 February 1983
 Bibcode:
 1983wsis.rept.....L
 Keywords:

 Arrays;
 Chips (Electronics);
 Electronic Packaging;
 Microprocessors;
 Very Large Scale Integration;
 Wafers;
 Electric Wire;
 Fault Tolerance;
 Graph Theory;
 Layouts;
 Network Synthesis;
 Planar Structures;
 Silicon;
 Traveling Salesman Problem;
 Electronics and Electrical Engineering