A carrier recovery closed loop implementation in high velocity PSK modems by digital techniques

The use of conventional carrier recovery closed loops, in modems implemented through digital technics, is made difficult by the volume of signal processing that they require. An alternative solution in which the baseband componenus used for detecting the phase error are under-sampled was already presented. But, practical tests with this experimental carrier recovery closed loop revealed significant difficulties in order to obtain a satisfactory overall system performance. The insertion of a properly selected element in the closed loop can contribute significantly to the system stability. In this case, auxiliary elements are necessary to provide an efficient system performance, when in steady state, while obtaining a relatively fast transient response. Results obtained with the physical implementation of the model supported by digital techniques are presented.