Product assurance technology for procuring reliable, custom LSI/VLSI electronics

The effort described in this report initiates the development of a product assurance methodology that is intended to be used in the process of qualifying reliable, custom, CMOS-bulk integrated circuits obtained from silicon foundries using a set of composite layout rules. A major element in this methodology is the microelectronic test chip that is fabricated along with the integrated circuits. This report describes the effort involved in further developing the test-chip methodology. The major accomplishments include the development of a state-of-the-art parametric tester; the development of CMOS-bulk layout rules; the development of bulk test strips and test chips; the development of certain test structures, including the pinhole array capacitor for yield analysis and the split-cross-bridge resistor for process characterization; the development of a test-chip assembler software tool; the evaluation of two CMOS-bulk silicon foundry runs; and the identification of critical elements in procuring custom circuits from silicon foundries.