LSI (Large Scale Integrated) design for testability: Design, demonstration and testability analysis
Abstract
The objective of this effort was to demonstrate IBM Level Sensitive Scan Design methodology as an approach for improving the testability of military LSI/VLSI circuits. LSSD was demonstrated in an LSI component AP101C test bed to be a viable and attractive design approach for military LSI/VLSI components.
- Publication:
-
Final Report
- Pub Date:
- November 1983
- Bibcode:
- 1983ibm..reptR....G
- Keywords:
-
- Checkout;
- Computer Aided Design;
- Integrated Circuits;
- Large Scale Integration;
- Very Large Scale Integration;
- Data Bases;
- Flow Charts;
- Gates (Circuits);
- Life Cycle Costs;
- Logic Circuits;
- Military Technology;
- Requirements;
- Systems Engineering;
- Electronics and Electrical Engineering