Theoretical-experimental analysis of the effects of grain boundaries on the electrical properties of SOI (Silicon-On-Insulator) MOSFETS

This first annual report describes the development of a physical model for thin-film SOI (insulating substrates) MOSFET that will form the basis of a computer model for existing circuit simulation programs, e.g., SPICE. The model will thus enable computer simulation of SOI ICs, e.g., stacked CMOS, the prevalent basis for three dimensional ICs. The model characterizes the (effective) field-effect mobility, the threshold voltage, and the source-drain leakage of a MOSFET fabricated in recrystallized polysilicon-on-SiO2. The resulting physical model for the SOI MOSFET describes the influence of the grain boundaries and defects in the channel on the electrical characteristics of the transistor in terms of its properties, e.g., the channel length, the doping density, the film and oxide thicknesses, and the grain-boundary trap density. Such a model is essential in the optimization of the SOI technology and of the designs of SOI MOSFETs and ICs. It is also useful in developing grain-boundary passivation techniques, which we propose to do perhaps in the second year of this project.