Development of a process for manufacturing high voltage CMOS circuits and of a technology for gold bump plating for use in integrated display systems

High voltage CMOS circuits and gold bump plating technologies for large area color display systems are considered. Based on a market survey of LCD driver chips a circuit with 20 V output voltage was designed and successfully tested. Bump technology investigations involved the selection of the metallurgical system, the resist technology, the electroplating technique and the metal etching. Two process alternatives compatible with CMOS products are proposed. The use of Ti-Pd-An and Ti-Ni systems as intermediate layer fulfil the requirements. The Ti-Ni system presents cost advantages.