Technology for LSI circuits combining integrated injection logic and bipolar transistors

Large scale integrated circuits combining integrated injection logic (I2L) and bipolar circuits are described. By shrinking the lateral dimensions of the I2L-gates the packing density is increased from 230 to 640 gates/sqmm. Some I2L-Logic and bipolar transistors with breakdown voltage 30 V were combined. For compact integrated circuits a gate array with 700 I2L-gates and bipolar periphery circuits was developed and tested. For short time realization of special mask designs a computer assisted design system was prepared. A high speed I2L allows 6 nsec delay time. The speed power product is 0,1 pJ at low currents and 0,5 pJ at 10 nsec delay. The packing density is 900 gates/sqmm.