Impact of electrostatics on IC (Integrated Circuit) fabrication
Abstract
Integrated circuit fabrication processes inherently involve materials with a high propensity of triboelectric charge generation. This report details the results of a study in which the intent was: (1) to determine how electrostatic charges can catastrophically dame integrated circuits during their fabrication, and (2) to investigate the effect these charges have on individual fabrication processes. Possible reliability implications of the presence of electric charges during fabrication are also hypothesized. An experiment was also carried out to determine the susceptibility of IC's in wafer form. In these tests, devices were stressed at various levels and then electrically tested to determine their functionality. Additionally, the susceptibility modes of devices in wafer form were compared to those in packaged form.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- September 1983
- Bibcode:
- 1983STIN...8419713D
- Keywords:
-
- Electrostatic Charge;
- Fabrication;
- Integrated Circuits;
- Comparison;
- Electric Discharges;
- Electrostatics;
- Reliability;
- Tribology;
- Wafers;
- Electronics and Electrical Engineering