A simple double error correcting BCH codes
Abstract
With the availability of various cost effective digital hardware components, error correcting codes are realized in hardware in simpler fashion than was hitherto possible. Instead of computing error locations in BCH decoding by Berklekamp algorith, syndrome to error location mapping using an EPROM for double error correcting BCH code is described. The processing is parallel instead of serial. Possible applications are given.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- July 1983
- Bibcode:
- 1983STIN...8335198S
- Keywords:
-
- Bch Codes;
- Computer Storage Devices;
- Matrices (Mathematics);
- Parallel Processing (Computers);
- Algorithms;
- Chips (Electronics);
- Cost Effectiveness;
- Error Correcting Codes;
- Mathematical Models;
- Communications and Radar