Heavy-ion induced single event upsets in a bipolar logic device

Heavy ion test results are presented for a bipolar logic device of moderate complexity. Devices of this type call for the implementation of special techniques for testing circuits of varying upset sensitivity. In contrast to similar MOS devices, problems are encountered in interpreting the test data. It is noted that the test results agree in part with predictions based on a qualitative analysis of subcircuits contained in this device. The tests are able to determine separately the upset vulnerability of two independent subcircuits present on the chip. In spite of this partial agreement, the results are seen as raising numerous questions when examined in the light of the relatively complex device geometry and physical properties. It is believed that no reliable models exist that can predict with any degree of credibility the upset rate of bipolar devices from a knowledge of the device circuit parameters, either obtained empirically from electrical tests or calculated on the basis of geometry and physical process features.