A versatile CMOS rate multiplier/variable divider

A versatile CMOS rate-multiplier/variable-divider integrated circuit that delivers an optimally spaced output signal is presented. The paper includes a comparison of the commonly used rate-multiplication scheme and the accumulator rate-multiplier principle. It is shown that this principle always delivers the best possible digital approximation of a regular signal, but it is inherently slower. The design considerations for speed improvement are described, together with a scheme that leads to the special feature of a programmable denominator. In this case, the circuit can be used as, for example, a binary rate multiplier, BCD rate multiplier, and variable divider, etc. Cascading possibilities are shown, and some application areas are given. The circuit is ideally suited for use as a microprocessor compatible peripheral circuit in digital control systems.