Novel vertical GaAs FET structure with submicrometre source-to-drain spacing

In connection with a study concerning the feasibility of the development of sub 1/2 micron source-to-drain spaced FET's, a vertical 1/2 micron GaAs FET structure was produced. Difficulties regarding the technical implementation of theoretical structures had been related to the placement of a gate contact very close to the source and drain contact. In the present study, as a gate contact, a lossy insulator metal-insulator-semiconductor (MIS) contact has been incorporated into an already existing 0.5 micron vertical GaAs FET structure. The first tests indicate that the lossy insulator gate contact represents an attractive alternative to the Schottky contact for sub 1/2 micron source-to-drain spaced transistors.