CMOS logic circuit optimum design for radiation tolerance
Abstract
CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36 percent greater than for the three-input NOR. The gate area for the optimized NAND is about three times smaller than that for the optimized NOR.
- Publication:
-
Electronics Letters
- Pub Date:
- November 1983
- DOI:
- 10.1049/el:19830664
- Bibcode:
- 1983ElL....19..977H
- Keywords:
-
- Circuit Reliability;
- Cmos;
- Ionizing Radiation;
- Logic Circuits;
- Logic Design;
- Radiation Tolerance;
- Gates (Circuits);
- Metal Oxide Semiconductors;
- Optimization;
- Electronics and Electrical Engineering