Conversion of algorithms to custom integrated circuit devices

This project studies the way in which high level functional descriptions can be converted through a succession of representations by means of local transformations to a final mask specification. A major focus of the work is the determination of the form of these representations, as well as the nature of the transformations between them. Major emphasis has been devoted to the specification of high level algorithms, in a way such that performance variations can be studied, either through the use of constraint representations, or by use of conflict avoidance schemes that permit the systematic exploration of various degrees of parallelism inherent in an algorithm. Following architectural determination through exploration of space/time tradeoffs, various well-formedness tests are executed, including topology extraction, circuit extraction logic verification, design rule checking, timing analysis, and circuit simulation. In addition, testability is characterized and test vectors are generated. Following the well formedness checks, which are under development. Using these techniques it is possible to generate modules, ascertain their well formedness, connect them into clusters at the next higher level of the overall system hierarchy, and continue interatively until the entire design is complete.