Advanced electrical test techniques for LSI microcircuits

An investigation was conducted to determine the feasibility of developing new LSI test techniques using test parameters that could be directly related to the physical structure of the device. In addition, a test technique capable of detecting potential failures or increasing safe operating margins was highly desirable. Two test methods were developed and evaluated for static RAMs: (1) Flip flop cell unbalance detection and (2) time-dependent failure detection. Three test techniques were evaluated for dynamic RAMs: (1) chip enable pulse width, (2) V-BUMP, and (3) refresh time. The memory cell flip flop unbalance parameter did not correlate with any device degradation or failure under life test conditions. However the unbalance detection technique was found to be useful in detecting functionally tested time-dependent failures. The chip enable high test with a maximum pulse width, as well as with a minimum pulse width, was determined to be highly useful in evaluating the drive capability margin of the clocked dynamic circuits. The V-BUMP test for checking the sense amplifier's ability to discriminate between Os and ls in the memory cell was determined to be a highly effective safe-margin testing technique. It was found that refresh time tests at room temperatures are ineffective in screening marginal parts, therefore such tests should be accomplished at high ambient temperatures. None of the three test parameters for dynamic RAMs was able to be correlated with degradation or life test failure.