New lower bound techniques for VLSI
Abstract
In this paper, crossing number and wire area arguments are used to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, an Nnode planar graph which has layout are theta(N log N) and maximum edge length theta(N(1/2)/log(1/2)N), an Nnode graph with an theta(x 1/2)separator which has layout area theta(N log(2)N) and maximum edge length theta(N(1/2)logN/loglogN), and an Nnode graph with an theta(x(11/r)separator which has maximum edge length theta(N(11/r) for any r > or = .3.
 Publication:

NASA STI/Recon Technical Report N
 Pub Date:
 August 1982
 Bibcode:
 1982STIN...8319003L
 Keywords:

 Chips (Electronics);
 Computer Networks;
 Integrated Circuits;
 Edges;
 Graphs (Charts);
 Grids;
 Mathematical Models;
 Electronics and Electrical Engineering