The configurable, highly parallel (CHiP) approach for signal processing applications
Abstract
A VLSI design methodology, built around the CHiP architecture, is described. The switch lattice of the CHiP architecture is the primary design abstraction. The lattice is a flexible design medium with constraints that mirror those of raw silicon. An eight point pipelined Fast Fourier Transform design, used as a running example, is of independent interest for its locally connected layout.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- May 1982
- Bibcode:
- 1982STIN...8313341S
- Keywords:
-
- Algorithms;
- Computer Aided Design;
- Fast Fourier Transformations;
- Integrated Circuits;
- Signal Processing;
- Architecture (Computers);
- Independent Variables;
- Microprocessors;
- Silicon;
- Switching Circuits;
- Communications and Radar