Processor displacement: An area-time trade-off method for VLSI design

Direct VLSI implementation of pipelined (systolic) processor arrays can lead to an over parallelized design causing the chip to have unused or underutilized area. Processor displacement design is a methodology that provides a spectrum of designs with differing time-area trade offs. The methodology is motivated, presented in detail, and illustrated by several examples. Direct experience for the Transitive Closure and Dynamic Programming systolic arrays is presented.