Portable design rules for bulk CMOS
Abstract
It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.
- Publication:
-
NASA STI/Recon Technical Report A
- Pub Date:
- October 1982
- Bibcode:
- 1982STIA...8328150G
- Keywords:
-
- Cmos;
- Network Synthesis;
- Production Engineering;
- Technology Utilization;
- Very Large Scale Integration;
- Circuit Reliability;
- Design Analysis;
- Fabrication;
- Layouts;
- Reliability Engineering;
- Sos (Semiconductors);
- Electronics and Electrical Engineering