Power Mosfets.

A power MOSFET, a semiconductor power device based on modern IC technology, can offer some unique characteristics: high gain with high breakdown voltage, low on-resistance in low voltage devices, and fast switching speed. In response to a fast-growing interest and the need for better understanding, modeling, and design techniques, this thesis is a study of many aspects of power MOSFETs. Analytical models of all components of on-resistance are developed for both linear and cellular source geometries. Lower on-resistance can result from cellular geometries. Calculated results agree with experimental data. Based on these models, a design procedure to achieve minimum on-resistance is proposed. The dimension of source regions should first be minimized. The spacing between source cells is then varied until the resistance is minimized. Inherent limits on the switching speeds and losses of vertical power MOSFETs due to the drain capacitance are analyzed. While the drain capacitance is a function of the drain voltage, it is shown that speeds can be calculated with constant average capacitance. The per-cycle switching loss is similarly analyzed. Graphs of speeds and switching losses are presented as design aids. A model for the phenomenon of second breakdown in vertical power MOSFETs involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and the MOS body bias effect is proposed. This model is compared with experiments on four-terminal V-groove test devices in which the base can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. A novel structure of power MOSFETs is proposed for low voltage applications where the on-resistance is the main concern. Theoretical analysis shows that this structure can result in many times smaller on-resistance than conventional structures. A fabrication procedure is proposed. The critical step, i.e., the deep vertical etching of silicon, has not yet been developed.