The organization of circuit analysis on array architectures

The organization of a circuit analysis program on a computer configuration with additional hardware working in parallel to produce more output is discussed. The structure of the program is addressed, and a parallel algorithm is derived. A speedup analysis is presented, and a special purpose computer and its organization are described. The job and the parallel computer are combined into the scheduling model which uses software to optimally match the resources of the special purpose computer with resource needs. The task of solving the set of linear equations resulting from the discretized and linearized circuit equations is decomposed into tasks. Scheduling is demonstrated for the parallel solution of the set of linear equations, and some results of the decomposition and scheduling of the solution job for the set of linear equations are presented.