GaAs FET circuits handle high power. V - Designers: Prepare for the GaAs FET age
Abstract
Bias design operating precautions for a GaAs FET circuit, with high power capabilities, are presented. Several small-signal devices connected in parallel comprise power GaAs FETs, and a Schottky gate is used, with typical gate lengths in the range of 0.5-1.0 microns. Bias circuit design must avoid exceeding the gate current limit, and the gate and drain should be separately biased using a positive and negative dual power source, and adequate impedance must be included in the design. In addition, high current must be prevented from reaching the drain, and to accomplish this, negative voltage is applied to the gate first, then positive voltage is applied to the drain. GaAs FET reliability has been confirmed and they are being used at 20 GHz and higher, but device improvements are required.
- Publication:
-
Microwaves
- Pub Date:
- October 1982
- Bibcode:
- 1982MicWa..21...87B
- Keywords:
-
- Field Effect Transistors;
- Gallium Arsenides;
- Power Amplifiers;
- Transistor Amplifiers;
- Transistor Circuits;
- Circuit Diagrams;
- Gates (Circuits);
- Electronics and Electrical Engineering