Effect of CMOS miniaturization on cosmic-ray-induced error rate

A computer-aided modeling study for predicting the effect of scaling of VLSI circuitry and VHSIC on the induced upsets due to cosmic ray events encountered in space applications is described. The study was limited to CMOS/Bulk and CMOS/SOS memory cells being scaled down to VLSI geometries, which in commercially available equipment can possess 4 micron features. Scales in the range 4-0.4 micron were considered with regards to the bit-error rate to determine the charge threshold, the charge collection volume, and the probability that ions in the space environment interacting with the collection volume can produce the threshold charge for error. The computer model, CRIER, was employed to calculate the probability that ions approaching omnidirectionally, of a variety of types and energies, incident on a parallelepiped, can yield the energies necessary for charge upset.